Proton Direct Ionization in Sub-Micron Technologies: Numerical Method for RPP Parameter Extraction

Burn-in Temperature Projections for Deep Sub-micron Technologies

Burn-in faces significant challenges in recent CMOS technologies. The self-generated heat of each IC in a burn-in environment contributes to larger currents that can lead to further increase in junction temperatures, possible thermal run away, and yield-loss of good parts. Calculations show that the junction temperature is increasing by 1.45X/generation. This paper estimates the increase in jun...

Assessing SRAM test coverage for sub-micron CMOS technologies

This paper proposes a realistic memory fault probability model which predicts the probabilities of memory fault classes for a given process technology. Physical defects in the memory array are classified into five functional fault classes, which are stuck-at, stuck-open, transition, coupling, and data retention faults. Finally, the memory fault coverages of the known memory test algorithms are ...

Detection of Resistive Shorts in Deep Sub-micron Technologies

Current-based tests are the most effective methods available to detect resistive shorts. Delta IDDQ testing is the most sensitive variant and can handle off-state currents of 10-100 mA of a single core. Nevertheless this is not sufficient to handle the next generations of very deep sub-micron technologies. Moreover delay-fault testing and very-low voltage testing are not a real alternative for ...

Interconnect modeling and optimization in deep sub-micron technologies

Interconnect will be a major bottleneck for deep sub-micron technologies in the years to come. This dissertation addresses the communication aspect from a power consumption and transmission speed perspective. A model for the energy consumption associated with data transmission through deep sub-micron technology buses is derived. The capacitive and inductive coupling between the bus lines as wel...

ESD Protection Design Methodology in Deep Sub-micron CMOS Technologies